Concurrency in Multi-Core Processor Design

Abstract

It is possible to extend a microprocessor from a single core to a multiple cores by replicating the single core processor, and interfacing them to main memory bus via a bus arbitrator. With a multi-core processor, the possibilities for parallel programs are apparent, but the programmer must overcome those obstacles with lock based programming. Transactional Memory would provide a means for programmers to handle highly concurrent programming in a more forgiving environment. This thesis surveys these topics and discusses possible implementations in terms of the HERA architecture.